FIG. 1 shows plural high speed drivers 11 and 13 on a tri-state data bus 15. To avoid bus conflicts, only one of the drivers may be enabled, and thus have access to the bus, at any one time. Typically, this conflict avoidance is managed by an arbiter circuit 17 responsive to a clock signal CLK so as to provide output enable control signals OE1 and OE2 to the drivers. When one of the output enable control signals goes to a first state (e.g., high), the corresponding driver 11 or 13 becomes active, and data D1 or D2 received at that driver's input is applied at the driver's output to the bus line 15 as a data signal D1.sub.out or D2.sub.out, usually with some current amplification.
When output enable control signals go to a second state (e.g., low), the corresponding drivers are turned off, so that there is a high impedance between those drivers' inputs and outputs. Any data signals received at the inputs to such nonenabled or inactive drivers do not get put onto the bus. Thus it would seem that all that is needed to avoid conflicts would be to ensure that only one output enable signal is in the first state, so that only one driver is active at any one time. However, there is always some delay between transitions of the output enable signals and the change in active/inactive condition of the drivers. Moreover, in CMOS circuits it is typically the case that the drivers tend to turn on faster than they turn off. This is not a problem when the clock rate is sufficiently slow, because then a delay can be provided between switching off one output enable signal from high to low and a subsequent switching of another output enable signal from low to high, thereby compensating for the difference between a driver's turn on and turn off times. But as clock speeds increase this solution has become unworkable.
FIGS. 2A and 2B illustrate the problem. FIG. 2A shows a timing diagram representing the nearly ideal case that is achieved with relatively slow clocks (about 50 MHz or less). FIG. 2B is another timing diagram that shows what normally happens when faster clocks (greater than about 50 MHz) are used. In FIG. 2A, first the output enable control signal OE1 is high so that the first driver 11 in FIG. 1 is active. Thus, data D1 received at that driver's input is applied as an output signal D1.sub.out onto the bus line, so that whatever state (high or low) is the output data signal D1.sub.out, that state is also present on the bus line 15 forming a corresponding bus signal BUS. Next, at a clock edge or transition 19, or almost immediately thereafter, the output enable signal OE1 falls to a low state. This eventually turns the first driver off so that there is a high impedance between its input and output and no data output signal D1.sub.out will then be applied by the first driver to the bus. After OE1 has fallen low, but usually with some specified delay, the output enable control signal OE2 rises to a high state. (This may occur prior the first driver completing its turn off provided the second driver doesn't begin to turn on until after the first driver is off.) Again after some delay, the switch in the state of the output enable signal OE2 causes the second driver to turn on. As a result, an output data signal D2.sub.out is applied by the second driver to the bus, and the bus signal, BUS, again corresponds to a data signal, in this case D2.sub.out. The BUS signal thus represents data received successively from the several drivers with a very short interval 23 in which all drivers are momentarily off. However, as seen in FIG. 2B, for faster clock rates it is not always possible to provide an adequate delay between the pull down 25 of one output enable signal OE1 and the pull up 27 of another output enable signal OE2 to compensate for the difference in turn off and turn on times for the drivers. Thus, the second driver may turn on and begin to place its data D2.sub.out onto the bus (as seen at 29) before the first driver bus has turned off and thus while it is still providing data D1.sub.out to the bus (as seen at 31). Thus, the bus signal BUS may have an interval 33 where two drivers are in conflict and both attempting to place data on the bus. The bus is slow to stabilize because the two drivers are fighting each other, thereby increasing cycle times and slowing down the system. Further, with both driver enabled, there is unnecessarily high power consumption, particularly where one driver is trying to pull the bus up to a high logic state by sourcing current from a power supply line, while the other driver is trying to pull the bus down by sinking current to ground.
To avoid such conflicts, the prior conventional approach when using faster clocks has been to introduce a wait state as seen in FIG. 3. Transitions 35 and 37 in the output enable control signals OE1 and OE2 are separated by one clock cycle. This ensures that an active driver being disabled has sufficient time to turn off before the next driver begins to turn on. Having two drivers partially on is therefore avoided. However, a slow system with less bandwidth results due to the lost cycle.
An object of the invention is to provide a driver circuit that can avoid bus conflicts without losing a clock cycle even when using fast clocks.